1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof and more particularly, to a semiconductor device including alignment marks for measuring or estimating lithography overlay accuracy, and a fabrication method thereof.
2. Description of the Prior Art
Recently, miniaturization and integration have been progressing more and more. At present, ultra large-scale integrated semiconductor devices (ULSIs), for example, not only 256-Megabit Dynamic-Random-Access Memories (DRAMs) designed according to 0.25 micron design rule, but also 1 Gigabit DRAMs designed according to sub 0.25 .mu.m design rule, are being developed and examined. In order to deal with this progress in miniaturization and integration, the need for improving or enhancing the pattern-to-pattern (or, mask-to-mask) overlay or registration accuracy in photolithography processes has been becoming greater.
Typically, in semiconductor device fabrication, patterned layers made of metal, semiconductor, dielectric, and so on are successively formed so as to be stacked on a semiconductor substrate, thereby fabricating miniaturized semiconductor devices. In photolithography, it is required that patterns of geometric shapes in an upper level are accurately overlaid with respect to previously defined patterns of geometric shapes in a lower level. The required overlay accuracy for the patterns has been becoming stricter with progressing miniaturization of the semiconductor devices.
Conventionally, two typical measuring methods have been used to measure the overlay or placement error of the patterns. With a first conventional measuring method of this sort, rectangular patterns are formed at a fixed pitch in each layer in each semiconductor chip region. The overlapping or stacking state of the patterns in the two layers gives the degree of overlay error. The rectangular patterns are generally termed the "alignment vernier caliper" or alignment vernier".
With a second conventional measuring method of this sort, which is typical, a "lower alignment box mark" is formed in a lower layer and an "upper alignment box mark" is formed in an upper layer in each semiconductor chip region. The overlapping state of the alignment marks in the two layers gives the degree of overlay error. This method has been typically used in the automatic overlay measuring technique.
FIGS. 1A to 1F show a conventional fabrication method of a DRAM using the first conventional measuring method with the "alignment vernier caliper".
First, as shown in FIG. 1A, a field oxide layer 102 is selectively formed on a main surface of a silicon substrate 101 by a selective oxidation process or the like, defining active regions. For the sake of simplification of description, only one of the active regions is shown in FIGS. 1A to 1F, in which a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is formed.
Then, a gate oxide layer 104a is selectively formed on the exposed surface of the substrate 101 in the active region. Gate electrodes 103 are formed on the gate oxide layer 104a in the active region. Source/drain regions (not shown) are formed in the active region. Thus, two MOSFETs are adjacently formed in the active region, which serve as transfer transistors of the memory cell. These steps are performed by known processes.
Further, a silicon dioxide (SiO.sub.2) layer with a thickness of approximately 800 nm is formed on the whole substrate 101 to cover the MOSFETs by a Chemical Vapor Deposition (CVD) process, or the like. The bottom of the SiO.sub.2 layer is contacted with the exposed area of the substrate 104. The surface of the SiO.sub.2 layer is then planarized by a Chemical-Mechanical Polishing (OMP) process. Thus, an interlayer insulating layer 104 made of SiO.sub.2 is formed on the substrate 101.
The interlayer insulating layer 104 may be formed by a Boron-doped Phosphorsilicate Glass (BPSG) layer whose surface is planarized by a reflow or etch-back process.
A patterned resist mask 105 is formed on the interlayer insulating layer 104. This mask 105 has two square openings 105A for forming contact holes 106 of the source/drain regions and three rectangular openings 105Ba, 105Bb, and 105Bc for forming rectangular recesses 107, 108, and 109 serving as a lower alignment mark. The state at this stage is shown in FIG. 1A.
Using the mask 105, the interlayer insulating layer 104 and the gate oxide layer 104a are selectively removed by an anisotropically dry etching process, thereby forming the square contact holes 106 and the rectangular recesses 107, 108, and 109. The contact holes 106 are located at the corresponding positions to the openings 105A, respectively. The recesses 107, 108, and 109 are located at the corresponding positions to the openings 105Ba, 105Bb, and 105Bc, respectively. The size or width of the contact holes 106 is smaller than that of the recesses 107, 108, and 109. The state at this stage is shown in FIG. 1B.
Subsequently, to fill the contact holes 106, a polysilicon layer 110 with a thickness of 200 nm is deposited on the patterned interlayer insulating layer 104, as shown in FIG. 1C. Each of the contact holes 106 is entirely filled with the polysilicon layer 110. However, since the size (or width) of the recesses 107, 108, and 109 is smaller than that of the contact holes 106, the recesses 107, 108, and 109 are not filled with the polysilicon layer 110. The layer 110 covers the side walls of the recesses 107, 108, and 109 and the exposed surface of the substrate 101. Voids are generated in the respective recesses 107, 108, and 109. The state at this stage is shown in FIG. 1C.
The polysilicon layer 110 thus deposited is then etched back by a dry etching process until the surface of the interlayer insulating layer 104 is exposed. Thus, the polysilicon layer 110 existing in the contact holes 106 is selectively left, thereby forming polysilicon plugs 111. At the same time, the polysilicon layer 110 existing in the recesses 107, 108, and 109 is selectively left, thereby forming polysilicon sidewalls 112. The state at this stage is shown in FIG. 1D.
Further, to form the lower electrodes of the storage capacitors for the MOSFETs, a polysilicon layer 113 with a thickness of approximately 800 nm is deposited on the interlayer insulating layer 104 over the entire substrate 101 by a CVD process. The state at this stage is shown in FIG. 1E.
Depressions are generated in the surface of the polysilicon layer 113 due to the underlying recesses 107, 108, and 109.
To pattern the polysilicon layer 113 thus deposited, a photoresist layer is uniformly formed on the layer 113. Then, to pattern the polysilicon layer 113, the layer 113 is subjected to reduction projection exposure and development processes. The photoresist layer thus patterned has square patterns 114 for forming the lower electrodes, and rectangular patterns 115, 116, and 117 for serving as an upper alignment mark. The state at this stage is shown in FIG. 1F.
The patterns 115, 116, and 117 are located in the depression of the polysilicon layer 113 right over the corresponding recesses 107, 108, and 109, respectively.
The rectangular recesses 107, 108, and 109 in the interlayer insulating layer 104 serve as the lower alignment mark. In other words, these recesses 107, 108, and 109 serve as a main scale of the alignment vernier caliper. The overlying rectangular patterns 115, 116, and 117 serve as the upper alignment mark. In other words, these patterns 115, 116, and 117 serve as a vernier scale of the alignment vernier caliper.
The overlay accuracy of the photoresist patterns 114 is determined or estimated by reading the overlapping state of the patterns 115, 116, and 117 with the corresponding recesses 107, 108, and 109 with the use of an optical microscope. Specifically, the overlapping state of the pattern 115 with the underlying recess 107 is checked. Similarly, the overlapping state of the pattern 116 with the underlying recess 108, and the overlapping state of the pattern 117 with the underlying recess 109 is checked.
Next, the use of the lower and upper alignment marks is explained in more detail with reference to FIGS. 2 and 3.
In FIG. 2, a rectangular mark 121, which corresponds to the recess 107, 108, or 109 in the interlayer insulating layer 104, serves as the lower alignment mark. A rectangular mark 122, which corresponds to the pattern 115, 116, or 117 on the polysilicon layer 113, serves as the upper alignment mark.
To measure or estimate the overlay error of the upper mark 122 with respect to the lower mark 121, the distance X between the edge 121a of the mark 121 and the opposing edge 122a of the mark 122 is measured with the use of an optical microscope. At the same time, the distance Y between the edge 121b of the mark 121 and the opposing edge 122b of the mark 122 is also measured. The overlay error is estimated by the existence or absence of the difference between the distances X and Y.
Next, the measurement principle of the alignment vernier caliper is explained with reference to FIG. 3.
In FIG. 3, as the lower alignment mark, first, second, third, fourth, and fifth rectangular patterns 123, 124, 125, 126, and 127 are formed in parallel. These patterns 123, 124, 125, 126, and 127 are arranged along a straight line at an equal pitch p in a lower level. On the other hand, as the upper alignment mark, first, second, third, fourth, and fifth rectangular patterns 128, 129, 130, 131, and 132 are formed in parallel. The patterns 128, 129, 130, 131, and 132 are arranged along the same straight line at an equal pitch q in an upper level.
It is seen from FIG. 3 that the overlapping state of the second mark 129 with the corresponding second mark 124 is best, because the mark 129 is located at the center of the mark 124, in other words, the distances X and Y in FIG. 2 are equal. Therefore, if the pitches p and q satisfy the equation, q=p+0.025 .mu.m, it is determined that the overlay error is +0.025 .mu.m in this case. If the overlapping state of the third (i.e., center) mark 129 with the corresponding third (i.e., center) mark 124 is best, the overlay error is measured as 0.
Then, by setting the compensation parameter of the exposure system to a value of +0.025 pm, the overlay accuracy can be improved.
The processes after the step of FIG. 1F may be performed by known, popular processes. Therefore, the explanation of these processes is omitted here for simplicity.
With the conventional fabrication method shown in FIGS. 1A to 1F, a problem exists in that reading or recognition of the upper and lower alignment marks with the optical microscope is very difficult. This difficulty increases with increasing miniaturization of semiconductor devices.
Specifically, after the polysilicon layer 110 is deposited on the patterned interlayer insulating layer 104 to fill the contact holes 106, the polysilicon plugs 111 are formed in the respective contact holes 106 by the etching back process. Therefore, polysilicon sidewalls 112 are inevitably formed in the recesses 107, 108, and 109, respectively. Subsequently, the voids in the recesses 107, 108, and 109 are filled with the polysilicon layer 113 for the lower electrode of the storage capacitor.
Accordingly, each edge of the lower alignment mark is doubled. Specifically, as shown in FIG. 4, the edge 121a in FIG. 2 appears to be two adjacent edges 119a and 120a, and the edge 121b in FIG. 2 appears to be two adjacent edges 119b and 120b. This is because the edges 120a and 120b of the sidewalls 112 are adjacent located to the corresponding top edges 119a and 119b of the recesses 107, 108, and 109, respectively. The doubled edges 119a and 120a and 119b and 120b make it very difficult to visually read out the overlapping state between the upper and lower alignment marks.
Also, due to the existence of the recesses 107, 108, and 109, some depressions are generated in the surface of the polysilicon layer 113, as shown in FIG. 1E. The patterns 115, 116, and 117 of the photoresist layer are located in the depressions, respectively. Therefore, the patterns 115, 116, and 117 tend to have distorted shapes, which increases the difficulty in reading or measuring of the upper and lower alignment marks.
FIG. 5 shows the second conventional measuring method described previously.
In FIG. 5, similar to the device shown in FIGS. 1A to 1F, the interlayer insulating layer 104 is formed on the semiconductor substrate 101. However, unlike the device of FIGS. 1A to 1F, recess 141 has the shape of a rectangular box, the size or width of which is larger than that of the recesses 107, 108, and 109. The four inner walls of the recess 141 are covered with the four polysilicon sidewalls 142, respectively. The bottom wall of the recess 141 is formed by the substrate 101. The recess 141 serves as an "outer alignment box mark".
A polysilicon layer 144 for forming the lower electrode of the storage capacitor is formed on the patterned interlayer insulating layer 104. The layer 144 covers the bottom and side walls of the recess 141.
A pattern 145 of a photoresist layer is formed on the polysilicon layer 144. The pattern has the shape of a rectangular box, the size or width of which is smaller than that of the recess 141. The four outer side walls of the pattern 145 are apart from the opposing walls of the polysilicon layer 144. The bottom wall of the pattern 145 contacts the opposing wall of the polysilicon layer 144. The pattern 145 serves as an "inner alignment box mark".
The pattern 145 serving as the "inner box mark" is located in the recess 141 serving as the "outer box mark". In other words, the pattern 145 is entirely included in the "outer box mark".
By reading or measuring the distances between the four edges of the outer box mark (i.e., the recess 141) and the four opposing edges of the inner box mark (i.e., the pattern 145) thereto, the overlay error of the pattern 145 with respect to the recess 141 can be known.